The present invention relates to a control apparatus. In particular, the invention relates to a control apparatus operated with program data and enabling control sequence to be altered with ease and at a low cost.
Generally, in order to realize complicated sequence control all with a hardware configuration, an exclusive circuit for each sequence is needed, causing the cost to rise. Therefore, if a general-purpose control circuit is operated with software, and different types of sequence control use this control circuit in common, a rise of cost can be prevented.
For example, an optical disc apparatus is disclosed in JP-A-188292/1998. In this publication, when a focus jump for moving the focal point of a laser beam between the recording layers of a disk is made, a DSP (Digital Signal Processor) (hereinafter referred to as a control apparatus), which operates with the program stored in a ROM (Read Only Memory), detects the moving speed of an optical pickup. When the moving speed is zero, a focus jump is made. This can realize a stable focus jump. Thus, an optical disc apparatus needs, in addition to a focus jump, various types of sequence control including a track jump for moving the focal point of a laser beam between the tracks, and it is necessary to reduce the cost. This example will be described with reference to the block diagram shown in FIG. 2.
FIG. 2 is a block diagram of an optical disc apparatus, which includes a large-scale integration circuit (LSI) 1 and a system controller 6. The LSI 1 consists of a control circuit 2, a ROM 3, a parameter memory 4 and a servo circuit 5.
The control circuit 2 contains an accumulator and a timer, supplies program addresses to the ROM 3 and operates in accordance with the program data read from the ROM 3. The ROM 3 is a program memory in which program data is stored, and supplies the control circuit 2 with the program data according to the program addresses supplied from the control circuit 2. The control circuit 2 reads data from and writes data in the parameter memory 4, in which the parameters required for various types of sequence control are set up. The memories may be a SRAM (Static Random Access Memory) and a flip flop circuit. The servo circuit 5 is a servo block including an A/D converter, a compensation circuit, a D/A converter and a jump circuit. The A/D converter carries out analog-digital conversion of the focus error signals and the tracking error signals supplied from a head amplifier (not shown). The compensation circuit compensates a phase and a gain for the output from the A/D converter. The D/A converter carries out digital-analog conversion of the output signal from the compensation circuit. The jump circuit outputs a jump pulse. The servo circuit 5 is connected to the head amplifier and a driver (not shown) The system controller 6 sends a processing request to the control circuit 2, and receives from it a signal which indicates whether processing is completed or not.
The control circuit 2 is configured to operate in accordance with the program data output from the ROM 3, and the operation is programmable. The control circuit 2 constantly monitors a processing request from the system controller 6. If the system controller 6 outputs a processing request, the control circuit 2 operates in accordance with the request.
The sequence control of the servo circuit 5 is performed by the control circuit 2, which operates in accordance with the software stored in the ROM 3. This makes it possible to use a common hardware configuration even for different types of sequence control, thereby lowering the cost. The ROM 3 can reduce the manufacturing cost by using a mask ROM.
On the other hand, advanced semiconductor technology has made it possible to mount an analog circuit, a digital circuit, a memory circuit, etc. in a single LSI, making it possible to reduce the number of parts for the production of apparatus using LSIs and lower the electric power. However, if the ROM 3, which is a program memory, is mounted inside the LSI, the software cannot be rewritten. This cannot flexibly cope with problems on the sequence control and functional extension. If the software needs to be altered, the LSI must be remanufactured, which leads to an increase of a development term.
If the program memory is a SRAM, the software can be easily rewritten. However, this causes a cost rise because a SRAM is larger in circuit scale than a ROM.
Another ROM that can be rewritten is an EEPROM (Electrically Erasable Programmable Read Only Memory). However, it is difficult to manufacture SDRAMs (Synchronous Dynamic Random Access Memories) and EEPROMs in the same manufacturing process by using the present LSI manufacturing technology. Consequently, EEPROMs are not suitable for LSIs for specific use (ASIC: Application Specific IC), in many of which SDRAMs are mounted.
If an RISC (Reduce Instruction Set Computer) type microcomputer with a simple circuit configuration is used for the control circuit 2, it is necessary to read program data for every clock. In this case, since the access speed of an SDRAM is slow compared with a SRAM and a ROM, the SDRAM is not suitable as a program memory of the RISC type microcomputer.
For the reasons stated above, it was difficult to rewrite the data in the program memory contained in the LSI with ease and at a low cost.
On the other hand, JP-A-182153/1998 discloses another technology which can revise a program easily. The revised program stored in an external EEPROM is beforehand downloaded to a RAM. The program that needs changing uses the data stored in the RAM, while the program that does not need changing uses the data stored in the ROM.
In JP-A-182153/1995, however, the following points were not considered. When there are two or more sub routines to be altered, the program to be downloaded may be larger than the memory size of the RAM. The publication cannot cope with the case. If the system is configured to alter one sub routine to be revised to run and then to download another sub routine to be revised next, the control circuit cannot perform other processing while the sub routine after the second is being downloaded because the control circuit is compelled to concentrate on downloading.
In the optical disc apparatus, the control circuit may perform various types of regular processing while waiting for the processing request from the system controller. This lessens hardware configurations. For example, while the focus servo is operating regularly, it is monitored whether the absolute value of a focus error signal is less than a predetermined voltage or not. When the absolute value becomes more than the predetermined voltage, the state is judged out of focus, and then, the interruption signal that indicates the state out of focus is output to the system controller. In this case, the cost can be reduced because there is no need for an additional comparison circuit that compares the focus error signal with the predetermined voltage.
However, if the download processing needs to be performed while the focus servo is operating regularly, the control circuit cannot detect the above-mentioned out-of-focus state. Thus, if the control circuit is configured to perform the download processing while the optical disk apparatus is operating, it becomes inconvenient for the regular processing to be performed.
JP-A-098119/1991 discloses a method of altering program data by choosing the output data from a RAM if a program address is a predetermined address. This method needs an address comparison circuit, and a cost rise is caused if the address width is large. Moreover, since this is a method of replacing one word to be altered with one revised word, the method cannot cope with the addition and deletion of programs.